Area-optimal cache coherent protocol for many-core network-on-chip

Cache coherence support is a major component in network-on-chip (NoC) systems which consist of multiple processing cores or elements as it is essential to ensure that the changes in shared memory are well communicated between all cores. Due to the nature and architecture of NoC, cache coherence prot...

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Main Author:	Ng, Wai Kin
Format:	Thesis
Language:	English
Published:	2022
Subjects:	TK Electrical engineering Electronics Nuclear engineering
Online Access:	http://eprints.utm.my/id/eprint/99547/1/NgWaiKinMSKE2022.pdf
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spelling	my-utm-ep.995472023-02-28T08:24:35Z Area-optimal cache coherent protocol for many-core network-on-chip 2022 Ng, Wai Kin TK Electrical engineering. Electronics Nuclear engineering Cache coherence support is a major component in network-on-chip (NoC) systems which consist of multiple processing cores or elements as it is essential to ensure that the changes in shared memory are well communicated between all cores. Due to the nature and architecture of NoC, cache coherence protocols can have different characteristics in terms of various design consideration factors such as performance, area and power. Since the number of cores are expected to increase more in computing systems in the future, these factors need to be appropriately considered for scalability during design process so that the implementation will be feasible and be able to maintain an effectiveness of the system design. Cache coherence protocols proposed for NoC systems such as the directory protocol, Hammer and token protocol each has different impact on execution performance and design cost associated, due to the different mechanism used to maintain the cache coherency. In this project, these protocols are implemented and simulated using the GEM5 simulator and the area overhead is estimated using the Multicore Power, Area, and Timing (McPAT) framework. The simulation using blackscholes, fluidanimate and bodytrack application from the Princeton Application Repository for Shared-Memory Computers (PARSEC) benchmark shows that the Hammer protocol outperforms all evaluated protocols in execution performance, but the area overhead required for the protocol is also the largest. Token protocol, on the other hand, provide a significant lower performance, which is 2% lower compared to the Hammer protocol, but its 7% area overhead incurred is the lowest among all protocols. This shows that token protocol exhibits the best scalability for area overhead with increasing number of processing cores while providing moderate performance in terms of execution time. 2022 Thesis http://eprints.utm.my/id/eprint/99547/ http://eprints.utm.my/id/eprint/99547/1/NgWaiKinMSKE2022.pdf application/pdf en public http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:149967 masters Universiti Teknologi Malaysia, Faculty of Engineering - School of Electrical Engineering Faculty of Engineering - School of Electrical Engineering
institution	Universiti Teknologi Malaysia
collection	UTM Institutional Repository
language	English
topic	TK Electrical engineering Electronics Nuclear engineering
spellingShingle	TK Electrical engineering Electronics Nuclear engineering Ng, Wai Kin Area-optimal cache coherent protocol for many-core network-on-chip
description	Cache coherence support is a major component in network-on-chip (NoC) systems which consist of multiple processing cores or elements as it is essential to ensure that the changes in shared memory are well communicated between all cores. Due to the nature and architecture of NoC, cache coherence protocols can have different characteristics in terms of various design consideration factors such as performance, area and power. Since the number of cores are expected to increase more in computing systems in the future, these factors need to be appropriately considered for scalability during design process so that the implementation will be feasible and be able to maintain an effectiveness of the system design. Cache coherence protocols proposed for NoC systems such as the directory protocol, Hammer and token protocol each has different impact on execution performance and design cost associated, due to the different mechanism used to maintain the cache coherency. In this project, these protocols are implemented and simulated using the GEM5 simulator and the area overhead is estimated using the Multicore Power, Area, and Timing (McPAT) framework. The simulation using blackscholes, fluidanimate and bodytrack application from the Princeton Application Repository for Shared-Memory Computers (PARSEC) benchmark shows that the Hammer protocol outperforms all evaluated protocols in execution performance, but the area overhead required for the protocol is also the largest. Token protocol, on the other hand, provide a significant lower performance, which is 2% lower compared to the Hammer protocol, but its 7% area overhead incurred is the lowest among all protocols. This shows that token protocol exhibits the best scalability for area overhead with increasing number of processing cores while providing moderate performance in terms of execution time.
format	Thesis
qualification_level	Master's degree
author	Ng, Wai Kin
author_facet	Ng, Wai Kin
author_sort	Ng, Wai Kin
title	Area-optimal cache coherent protocol for many-core network-on-chip
title_short	Area-optimal cache coherent protocol for many-core network-on-chip
title_full	Area-optimal cache coherent protocol for many-core network-on-chip
title_fullStr	Area-optimal cache coherent protocol for many-core network-on-chip
title_full_unstemmed	Area-optimal cache coherent protocol for many-core network-on-chip
title_sort	area-optimal cache coherent protocol for many-core network-on-chip
granting_institution	Universiti Teknologi Malaysia, Faculty of Engineering - School of Electrical Engineering
granting_department	Faculty of Engineering - School of Electrical Engineering
publishDate	2022
url	http://eprints.utm.my/id/eprint/99547/1/NgWaiKinMSKE2022.pdf
_version_	1776100616775401472

Area-optimal cache coherent protocol for many-core network-on-chip

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