A parallel built-in self-test design for photon counting array

Test module’s architectures and methodologies that would maximize test capability to filter out faulty chip after fabrication is highly demanded for chip cost reduction. A high-speed frequency Built-in Self-test (BIST) module is playing an increasingly large part in overall efficiency and quality of...

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Main Author:	Png, Ricky Keh Jing
Format:	Thesis
Language:	English
Published:	2022
Subjects:	TK Electrical engineering Electronics Nuclear engineering
Online Access:	http://eprints.utm.my/id/eprint/99566/1/PngKehJingMSKE2022.pdf
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spelling	my-utm-ep.995662023-03-01T08:18:41Z A parallel built-in self-test design for photon counting array 2022 Png, Ricky Keh Jing TK Electrical engineering. Electronics Nuclear engineering Test module’s architectures and methodologies that would maximize test capability to filter out faulty chip after fabrication is highly demanded for chip cost reduction. A high-speed frequency Built-in Self-test (BIST) module is playing an increasingly large part in overall efficiency and quality of a test solution for testability (DFT). This project is proposing the design of a parallel BIST circuit for a 16x1 photon counting array using 180 nm CMOS technology to improve the fault coverage and reduce testing cost. Almost all the test modules are built into the chip, an external tester will need to provide a start signal for the BIST design to start the testing process. LFSR is used for pseudo-random pattern generator whereas MISR and SISR are used as the output compactors. The BIST design adopts signature analysis to determine faulty chip. The golden signature is produced and being stored in ROM for comparison after fabrication. BIST controller acts as a controller unit (CU) that sends the control signals to every BIST functional block in each state. The entire BIST design is then integrated into the photon counting system for validation and layout generation. This project used bottom-up approach by designing the modules of BIST blocks in SystemVerilog. Performances are then analysed and evaluated by using Synopsys Design Compiler, IC compiler and PrimeTime tools. From the finding, proposed BIST design has managed to enhance in terms of functional reliability and design controllability with the use of SystemVerilog. For test latency, chip area, maximum frequency and power consumption, the design shows great improvements by 67.67 %, 32.26 %, 15.20 % and 48.89 % respectively. 2022 Thesis http://eprints.utm.my/id/eprint/99566/ http://eprints.utm.my/id/eprint/99566/1/PngKehJingMSKE2022.pdf application/pdf en public http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:149747 masters Universiti Teknologi Malaysia, Faculty of Engineering - School of Electrical Engineering Faculty of Engineering - School of Electrical Engineering
institution	Universiti Teknologi Malaysia
collection	UTM Institutional Repository
language	English
topic	TK Electrical engineering Electronics Nuclear engineering
spellingShingle	TK Electrical engineering Electronics Nuclear engineering Png, Ricky Keh Jing A parallel built-in self-test design for photon counting array
description	Test module’s architectures and methodologies that would maximize test capability to filter out faulty chip after fabrication is highly demanded for chip cost reduction. A high-speed frequency Built-in Self-test (BIST) module is playing an increasingly large part in overall efficiency and quality of a test solution for testability (DFT). This project is proposing the design of a parallel BIST circuit for a 16x1 photon counting array using 180 nm CMOS technology to improve the fault coverage and reduce testing cost. Almost all the test modules are built into the chip, an external tester will need to provide a start signal for the BIST design to start the testing process. LFSR is used for pseudo-random pattern generator whereas MISR and SISR are used as the output compactors. The BIST design adopts signature analysis to determine faulty chip. The golden signature is produced and being stored in ROM for comparison after fabrication. BIST controller acts as a controller unit (CU) that sends the control signals to every BIST functional block in each state. The entire BIST design is then integrated into the photon counting system for validation and layout generation. This project used bottom-up approach by designing the modules of BIST blocks in SystemVerilog. Performances are then analysed and evaluated by using Synopsys Design Compiler, IC compiler and PrimeTime tools. From the finding, proposed BIST design has managed to enhance in terms of functional reliability and design controllability with the use of SystemVerilog. For test latency, chip area, maximum frequency and power consumption, the design shows great improvements by 67.67 %, 32.26 %, 15.20 % and 48.89 % respectively.
format	Thesis
qualification_level	Master's degree
author	Png, Ricky Keh Jing
author_facet	Png, Ricky Keh Jing
author_sort	Png, Ricky Keh Jing
title	A parallel built-in self-test design for photon counting array
title_short	A parallel built-in self-test design for photon counting array
title_full	A parallel built-in self-test design for photon counting array
title_fullStr	A parallel built-in self-test design for photon counting array
title_full_unstemmed	A parallel built-in self-test design for photon counting array
title_sort	parallel built-in self-test design for photon counting array
granting_institution	Universiti Teknologi Malaysia, Faculty of Engineering - School of Electrical Engineering
granting_department	Faculty of Engineering - School of Electrical Engineering
publishDate	2022
url	http://eprints.utm.my/id/eprint/99566/1/PngKehJingMSKE2022.pdf
_version_	1776100618681712640

A parallel built-in self-test design for photon counting array

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