APA引文

Li, F. (1997). A 9b 12.5Ms/s pipelined CMOS analog to digital converter design.

Chicago Style (17th ed.) Citation

Li, Feng. A 9b 12.5Ms/s Pipelined CMOS Analog to Digital Converter Design. 1997.

MLA引文

Li, Feng. A 9b 12.5Ms/s Pipelined CMOS Analog to Digital Converter Design. 1997.

警告：這些引文格式不一定是100％准確.