Modeling and analysis of semiconductor back-end assembly process /
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| Main Author: | |
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| Format: | Thesis Book |
| Language: | English |
| Published: |
1998.
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| Subjects: | |
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| LEADER | 00819cam a2200229 a 4500 | ||
|---|---|---|---|
| 001 | u428399 | ||
| 003 | SIRSI | ||
| 008 | 980826s1998 si v 00 1 eng m | ||
| 035 | |a ACF-6749 | ||
| 040 | |a UMM | ||
| 090 | |a TK7874 |b Jos | ||
| 100 | 1 | 0 | |a Joseph, Neethamol. |
| 245 | 1 | 0 | |a Modeling and analysis of semiconductor back-end assembly process / |c by Neethamol Joseph. |
| 260 | |c 1998. | ||
| 300 | |a ix, 70 leaves : |b ill. ; |c 30 cm. | ||
| 502 | |a Dissertation (M.Sc.) -- National University of Singapore, 1998. | ||
| 504 | |a Bibliography: leaves 70. | ||
| 650 | 0 | |a Integrated circuits |x Design and construction |x Simulation methods | |
| 650 | 0 | |a Semiconductors |x Design and construction. | |
| 948 | |a 29/08/1998 |b 13/10/1998 | ||
| 596 | |a 1 | ||
| 999 | |a TK7874 JOS |w LC |c 1 |i A507932214 |d 21/8/1999 |l STACKS |m P01UTAMA |n 1 |r Y |s Y |t TESIS |u 22/10/1998 | ||