APA引文

Leong, S. C. (2002). 1.0V, 10-bit, 20-MS/s pipelined analog-to-digital converter design.

Chicago Style (17th ed.) Citation

Leong, See Chuan. 1.0V, 10-bit, 20-MS/s Pipelined Analog-to-digital Converter Design. 2002.

MLA引文

Leong, See Chuan. 1.0V, 10-bit, 20-MS/s Pipelined Analog-to-digital Converter Design. 2002.

警告：这些引文格式不一定是100％准确.