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  1. 1
    Fault-tolerant capability of star-connected symmetrical six-phase induction machine with single and two isolated neutrals /
    by Wan Noraishah Wan Abdul Munim
    Published 2020
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  2. 2
    A built-in self-testable bit-slice processor /
    by Ibrahim Abubakr M.
    Published 1995
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  3. 3
    Development of a real time model based sensor fault tolerant control system /
    by Ernie Che Mid
    Published 2009
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  4. 4
    Low power clock tree synthesis for ASIC VLSI design /
    by Teng, Siong Kiong
    Published 2010
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  5. 5
    Lateral Diffused Metal Oxide Semiconductor (LDMOS) transistor Safe Operating Area (HCI-SOA) characterization under hot carrier injection /
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  6. 6
    Vision-assisted path planning system for die sorting in semiconductor industry /
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  7. 7
    Design and development of automatic pick and place system for integrated circuit semiconductor industry /
    by Prakas, Gopal Samy
    Published 2014
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  8. 8
    Characterizing the channel interface properties of vertical double-diffused metal-oxide semiconductor (DMOS) with charge pumping method /
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  9. 9
    Simulation framework of NBTI degradation in nano-scale p-mosfets from the perspective of hydrogen and non-hydrogen transport formalism /
    by Hanim Hussin
    Published 2015
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  10. 10
    Defectivity improvement in advanced processes and its investigation to negative bias temperature instabilities in High-K/Metal-Gate Deep-Submicron CMOS /
    by Yasmin Abdul Wahab
    Published 2015
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  11. 11
    Image segmentation for retriving encryption on integrated circuit in PCBA inspection /
    by Vigneswaran Thanabalan
    Published 2016
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  12. 12
    Electromigration damage in lead-free solder joints prepared using metallic nanoparticle doped flux /
    by Nasir, Muhammad
    Published 2017
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  13. 13
    In house electrostatic field meter calibration for improved ESD protection /
    by Husna Abdul Rahim
    Published 2019
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  14. 14
    Electrical test optimization for integrated circuit (IC) devices to improve productivity, cycle time and product cost /
    by Siva Raman
    Published 1997
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  15. 15
    Modeling of high-speed printed circuit board /
    by Fabian, Kung Wai Lee
    Published 1997
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  16. 16
    A VHDL implementation of BIST technique in UART design /
    by Mohd. Yamani Idna Idris
    Published 2002
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  17. 17
    Analysing random access memory chip yield performance /
    by Kam, Choy Sar
    Published 2000
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  18. 18
    A study of stress in backend metallization in ULSI devices /
    by Goh, Chia Lan
    Published 2006
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  19. 19
    VLSI floor planning optimization using genetic algorithm and cross entropy method /
    by Teoh, Angeline Szu Fern
    Published 2012
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  20. 20
    Development of design framework to overcome aging degradation of 16NM VLSI technology circuits /
    by Mahmoud, Mohamed Mounir
    Published 2013
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