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Universiti Malaya.
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VHDL (Computer hardware description language)
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Granting Institution:
Universiti Malaya.
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VHDL (Computer hardware description language)
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A VHDL implementation of BIST technique in UART design /
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Mohd. Yamani Idna Idris
Published 2002
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A scalable implementation of fully-connected neural networks using VHDL /
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Kuek, Chian Shiun
Published 2005
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Institution
Universiti Malaya
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Kuek, Chian Shiun
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Mohd. Yamani Idna Idris
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