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  1. 1
    Rescheduling in high-level syntheses /
    by Lim, Daniel Kok Yong
    Published 1997
    Subjects: “...Integrated circuits Very large scale integration Design and construction Data processing....”
    Thesis Book
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  2. 2
    Channel routing for rectilinear and octilinear routing models /
    by Lee, James Kok Kiong
    Published 1992
    Subjects: “...Integrated circuits Very large scale integration Design and construction Data processing....”
    Thesis Book
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  3. 3
    Scheduling in high level synthesis of VLSI circuits /
    by Xiong, Xing Rong
    Published 1996
    Subjects: “...Integrated circuits Very large scale integration Design and construction Data processing....”
    Thesis Book
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