Design Allocation And Scheduling Hardware Compiler For Digital Data Processing In FPGA

In this project, a high-level language and its automated compiler are proposed to automatically transform the language into a synthesizable RTL-level VHDL design. The proposed language, named as Simple Algorithmic Language for Hardware Design (SALH), is simple to use and featured single-assignment,...

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Main Author:	Hiew, Fu San
Format:	Thesis
Published:	2006
Subjects:	TK7800-8360 Electronics
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id	my-mmu-ep.1207
record_format	uketd_dc
spelling	my-mmu-ep.12072010-08-19T08:21:34Z Design Allocation And Scheduling Hardware Compiler For Digital Data Processing In FPGA 2006-10 Hiew, Fu San TK7800-8360 Electronics In this project, a high-level language and its automated compiler are proposed to automatically transform the language into a synthesizable RTL-level VHDL design. The proposed language, named as Simple Algorithmic Language for Hardware Design (SALH), is simple to use and featured single-assignment, in which it can reduce the coding lengthiness. 2006-10 Thesis http://shdl.mmu.edu.my/1207/ http://myto.perpun.net.my/metoalogin/logina.php masters Multimedia University Research Library
institution	Multimedia University
collection	MMU Institutional Repository
topic	TK7800-8360 Electronics
spellingShingle	TK7800-8360 Electronics Hiew, Fu San Design Allocation And Scheduling Hardware Compiler For Digital Data Processing In FPGA
description	In this project, a high-level language and its automated compiler are proposed to automatically transform the language into a synthesizable RTL-level VHDL design. The proposed language, named as Simple Algorithmic Language for Hardware Design (SALH), is simple to use and featured single-assignment, in which it can reduce the coding lengthiness.
format	Thesis
qualification_level	Master's degree
author	Hiew, Fu San
author_facet	Hiew, Fu San
author_sort	Hiew, Fu San
title	Design Allocation And Scheduling Hardware Compiler For Digital Data Processing In FPGA
title_short	Design Allocation And Scheduling Hardware Compiler For Digital Data Processing In FPGA
title_full	Design Allocation And Scheduling Hardware Compiler For Digital Data Processing In FPGA
title_fullStr	Design Allocation And Scheduling Hardware Compiler For Digital Data Processing In FPGA
title_full_unstemmed	Design Allocation And Scheduling Hardware Compiler For Digital Data Processing In FPGA
title_sort	design allocation and scheduling hardware compiler for digital data processing in fpga
granting_institution	Multimedia University
granting_department	Research Library
publishDate	2006
_version_	1747829316610162688

Design Allocation And Scheduling Hardware Compiler For Digital Data Processing In FPGA

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