Design Allocation And Scheduling Hardware Compiler For Digital Data Processing In FPGA

Design Allocation And Scheduling Hardware Compiler For Digital Data Processing In FPGA

In this project, a high-level language and its automated compiler are proposed to automatically transform the language into a synthesizable RTL-level VHDL design. The proposed language, named as Simple Algorithmic Language for Hardware Design (SALH), is simple to use and featured single-assignment,...

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书目详细资料
主要作者:	Hiew, Fu San
格式:	Thesis
出版:	2006
主题:	TK7800-8360 Electronics
标签:	添加标签没有标签, 成为第一个标记此记录!

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