Optimal modeling fill guide for improved interconnect performance
Chemical mechanical polishing (CMP) planarization process is an important step in fabrication for multi-layer metallization to create and design IC metallization and via interconnections. Fill synthesis methodologies are innovated by inserting dummy fill structures into the surrounding functional in...
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my-mmu-ep.54012014-03-27T02:43:53Z Optimal modeling fill guide for improved interconnect performance 2012-08 Yeo, Joel Yee Kiat TK7800-8360 Electronics Chemical mechanical polishing (CMP) planarization process is an important step in fabrication for multi-layer metallization to create and design IC metallization and via interconnections. Fill synthesis methodologies are innovated by inserting dummy fill structures into the surrounding functional interconnects to help reduced metal and oxide topography variations which caused by post-CMP planarization effects. In transition to ultra-deep sub-micron (UDSM) design technology nodes, fill synthesis increasingly causing performances impact to the interconnect design due to the parasitic capacitances induced by the dummy fill structures. Meeting CMP density design rules alone are no longer sufficient. Large spacing setbacks between functional interconnects and dummy fill structures are commonly used to minimize parasitic capacitance, however as design scaled further into the nanometer regime, a huge percentage of metal densities are sacrificed and achieving minimum density requirements in certain areas are not possible. A fill synthesis solution is proposed in this thesis to optimize and balance both of the requirements in-between chip performances and yield requirements. 2012-08 Thesis http://shdl.mmu.edu.my/5401/ http://vlib.mmu.edu.my/diglib/login/dlusr/login.php masters Multimedia University Faculty of Engineering |
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Multimedia University |
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TK7800-8360 Electronics |
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TK7800-8360 Electronics Yeo, Joel Yee Kiat Optimal modeling fill guide for improved interconnect performance |
| description |
Chemical mechanical polishing (CMP) planarization process is an important step in fabrication for multi-layer metallization to create and design IC metallization and via interconnections. Fill synthesis methodologies are innovated by inserting dummy fill structures into the surrounding functional interconnects to help reduced metal and oxide topography variations which caused by post-CMP planarization effects. In transition to ultra-deep sub-micron (UDSM) design technology nodes, fill synthesis increasingly causing performances impact to the interconnect design due to the parasitic capacitances induced by the dummy fill structures. Meeting CMP density design rules alone are no longer sufficient. Large spacing setbacks between functional interconnects and dummy fill structures are commonly used to minimize parasitic capacitance, however as design scaled further into the nanometer regime, a huge percentage of metal densities are sacrificed and achieving minimum density requirements in certain areas are not possible. A fill synthesis solution is proposed in this thesis to optimize and balance both of the requirements in-between chip performances and yield requirements. |
| format |
Thesis |
| qualification_level |
Master's degree |
| author |
Yeo, Joel Yee Kiat |
| author_facet |
Yeo, Joel Yee Kiat |
| author_sort |
Yeo, Joel Yee Kiat |
| title |
Optimal modeling fill guide for improved interconnect performance |
| title_short |
Optimal modeling fill guide for improved interconnect performance |
| title_full |
Optimal modeling fill guide for improved interconnect performance |
| title_fullStr |
Optimal modeling fill guide for improved interconnect performance |
| title_full_unstemmed |
Optimal modeling fill guide for improved interconnect performance |
| title_sort |
optimal modeling fill guide for improved interconnect performance |
| granting_institution |
Multimedia University |
| granting_department |
Faculty of Engineering |
| publishDate |
2012 |
| _version_ |
1747829570909765632 |