Design and implementation of a power efficient data-aware SRAM Array

In this project, two new power efficient data-aware cells have been proposed. In the proposed cells, dynamic power consumption is reduced by reducing the voltage swing on the respective bit-lines during write operation. In first proposed cell (7T BLC), an extra transistor is included in one of the p...

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Bibliographic Details
Main Author: Mah, Meng Seong
Format: Thesis
Published: 2013
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