Design and implementation of a power efficient data-aware SRAM Array

In this project, two new power efficient data-aware cells have been proposed. In the proposed cells, dynamic power consumption is reduced by reducing the voltage swing on the respective bit-lines during write operation. In first proposed cell (7T BLC), an extra transistor is included in one of the p...

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Main Author:	Mah, Meng Seong
Format:	Thesis
Published:	2013
Subjects:	TK Electrical engineering Electronics Nuclear engineering
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id	my-mmu-ep.5902
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spelling	my-mmu-ep.59022014-12-29T06:03:34Z Design and implementation of a power efficient data-aware SRAM Array 2013-04 Mah, Meng Seong TK Electrical engineering. Electronics Nuclear engineering In this project, two new power efficient data-aware cells have been proposed. In the proposed cells, dynamic power consumption is reduced by reducing the voltage swing on the respective bit-lines during write operation. In first proposed cell (7T BLC), an extra transistor is included in one of the pull down path of the 6T cell. This transistor is known as a tail transistor and its switching activity is controlled by the voltage at the bit-line. The second cell (9T cell) is designed after modifying the conventional 6T cell at the architecture level. The switching operation of the pull up and pull down transistors of the left inverter is controlled by an additional write signal. The value of the write signal is decided by the data to be written in the cell. The cell behaves dynamically during write operation due to a broken latch which allows the data to be flipped quickly. The read operation in the 9T cell is performed on a separate circuit which consists of two series connected transistors and one read bit-line. 2013-04 Thesis http://shdl.mmu.edu.my/5902/ http://library.mmu.edu.my/diglib/onlinedb/dig_lib.php masters Multimedia University Faculty of Engineering and Technology
institution	Multimedia University
collection	MMU Institutional Repository
topic	TK Electrical engineering Electronics Nuclear engineering
spellingShingle	TK Electrical engineering Electronics Nuclear engineering Mah, Meng Seong Design and implementation of a power efficient data-aware SRAM Array
description	In this project, two new power efficient data-aware cells have been proposed. In the proposed cells, dynamic power consumption is reduced by reducing the voltage swing on the respective bit-lines during write operation. In first proposed cell (7T BLC), an extra transistor is included in one of the pull down path of the 6T cell. This transistor is known as a tail transistor and its switching activity is controlled by the voltage at the bit-line. The second cell (9T cell) is designed after modifying the conventional 6T cell at the architecture level. The switching operation of the pull up and pull down transistors of the left inverter is controlled by an additional write signal. The value of the write signal is decided by the data to be written in the cell. The cell behaves dynamically during write operation due to a broken latch which allows the data to be flipped quickly. The read operation in the 9T cell is performed on a separate circuit which consists of two series connected transistors and one read bit-line.
format	Thesis
qualification_level	Master's degree
author	Mah, Meng Seong
author_facet	Mah, Meng Seong
author_sort	Mah, Meng Seong
title	Design and implementation of a power efficient data-aware SRAM Array
title_short	Design and implementation of a power efficient data-aware SRAM Array
title_full	Design and implementation of a power efficient data-aware SRAM Array
title_fullStr	Design and implementation of a power efficient data-aware SRAM Array
title_full_unstemmed	Design and implementation of a power efficient data-aware SRAM Array
title_sort	design and implementation of a power efficient data-aware sram array
granting_institution	Multimedia University
granting_department	Faculty of Engineering and Technology
publishDate	2013
_version_	1747829599680593920

Design and implementation of a power efficient data-aware SRAM Array

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