Investigation On Inter-Layer Dielectric Processed By Chemical Mechanical Polishing And Spin-On Dielectric For Complementary Metal-Oxide-Semiconductor Compatible Devices

Surface planarization of the thin film layers that constitute the interconnects in the backend process of integrated circuit (IC) has become a critical need with the increasing number of metal levels. Planarization, globally and locally, needs to be achieved using the most efficient planarization me...

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Main Author:	Mohd Saman, Rahimah
Format:	Thesis
Published:	2016
Subjects:	TK7800-8360 Electronics
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id	my-mmu-ep.7168
record_format	uketd_dc
spelling	my-mmu-ep.71682018-07-06T12:56:19Z Investigation On Inter-Layer Dielectric Processed By Chemical Mechanical Polishing And Spin-On Dielectric For Complementary Metal-Oxide-Semiconductor Compatible Devices 2016-07 Mohd Saman, Rahimah TK7800-8360 Electronics Surface planarization of the thin film layers that constitute the interconnects in the backend process of integrated circuit (IC) has become a critical need with the increasing number of metal levels. Planarization, globally and locally, needs to be achieved using the most efficient planarization methods available in the complementary metal oxide semiconductor (CMOS) IC fabrication industry. Spin-on dielectric (SOD) coating is a planarization method has long been used by the semiconductor industry. Since it uses liquid silica precursor, it creates particle defects either during storage or coating process because the evaporation of the liquid solvent leaves solid particles. The planarization degree is acceptable at sub-micron gap width but becomes worse at wider gap width. Chemical mechanical polishing (CMP) is another planarization method that is used by semiconductor industry for dielectric polishing. It is found that CMP is suitable to achieve desirable planarization with no particle defects as SOD, however it suffers microscratches, dishing, erosion and inefficient post-CMP cleaning. CMP planarization works by removing thin film using etching slurry and pressure applied on the wafer and it does not introduce any new dielectric material. This work is to investigate and improve the particle defects and the surface planarization of interlayer dielectric (ILD) using CMP, and also to investigate the electrical properties of the metal interconnect within the ILDs planarized by the SOD and CMP. 2016-07 Thesis http://shdl.mmu.edu.my/7168/ http://library.mmu.edu.my/diglib/onlinedb/dig_lib.php masters Multimedia University Faculty of Engineering
institution	Multimedia University
collection	MMU Institutional Repository
topic	TK7800-8360 Electronics
spellingShingle	TK7800-8360 Electronics Mohd Saman, Rahimah Investigation On Inter-Layer Dielectric Processed By Chemical Mechanical Polishing And Spin-On Dielectric For Complementary Metal-Oxide-Semiconductor Compatible Devices
description	Surface planarization of the thin film layers that constitute the interconnects in the backend process of integrated circuit (IC) has become a critical need with the increasing number of metal levels. Planarization, globally and locally, needs to be achieved using the most efficient planarization methods available in the complementary metal oxide semiconductor (CMOS) IC fabrication industry. Spin-on dielectric (SOD) coating is a planarization method has long been used by the semiconductor industry. Since it uses liquid silica precursor, it creates particle defects either during storage or coating process because the evaporation of the liquid solvent leaves solid particles. The planarization degree is acceptable at sub-micron gap width but becomes worse at wider gap width. Chemical mechanical polishing (CMP) is another planarization method that is used by semiconductor industry for dielectric polishing. It is found that CMP is suitable to achieve desirable planarization with no particle defects as SOD, however it suffers microscratches, dishing, erosion and inefficient post-CMP cleaning. CMP planarization works by removing thin film using etching slurry and pressure applied on the wafer and it does not introduce any new dielectric material. This work is to investigate and improve the particle defects and the surface planarization of interlayer dielectric (ILD) using CMP, and also to investigate the electrical properties of the metal interconnect within the ILDs planarized by the SOD and CMP.
format	Thesis
qualification_level	Master's degree
author	Mohd Saman, Rahimah
author_facet	Mohd Saman, Rahimah
author_sort	Mohd Saman, Rahimah
title	Investigation On Inter-Layer Dielectric Processed By Chemical Mechanical Polishing And Spin-On Dielectric For Complementary Metal-Oxide-Semiconductor Compatible Devices
title_short	Investigation On Inter-Layer Dielectric Processed By Chemical Mechanical Polishing And Spin-On Dielectric For Complementary Metal-Oxide-Semiconductor Compatible Devices
title_full	Investigation On Inter-Layer Dielectric Processed By Chemical Mechanical Polishing And Spin-On Dielectric For Complementary Metal-Oxide-Semiconductor Compatible Devices
title_fullStr	Investigation On Inter-Layer Dielectric Processed By Chemical Mechanical Polishing And Spin-On Dielectric For Complementary Metal-Oxide-Semiconductor Compatible Devices
title_full_unstemmed	Investigation On Inter-Layer Dielectric Processed By Chemical Mechanical Polishing And Spin-On Dielectric For Complementary Metal-Oxide-Semiconductor Compatible Devices
title_sort	investigation on inter-layer dielectric processed by chemical mechanical polishing and spin-on dielectric for complementary metal-oxide-semiconductor compatible devices
granting_institution	Multimedia University
granting_department	Faculty of Engineering
publishDate	2016
_version_	1747829658481590272

Investigation On Inter-Layer Dielectric Processed By Chemical Mechanical Polishing And Spin-On Dielectric For Complementary Metal-Oxide-Semiconductor Compatible Devices

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