VLSI Design Of A Bit Serial Arithmetic Logic Unit
The arithmetic logic unit (ALU) is designed to perform bit serial operation on two 8 bits input. In this project , a Very High Speed Integrated Circuit Hardware Description Language (VHDL) code is written using the Altera MAX+Plus II environment to design, compile and simulate for each operation in...
Saved in:
| Main Author: | |
|---|---|
| Format: | Thesis |
| Published: |
2003
|
| Subjects: | |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|