VLSI Design Of A Bit Serial Arithmetic Logic Unit

The arithmetic logic unit (ALU) is designed to perform bit serial operation on two 8 bits input. In this project , a Very High Speed Integrated Circuit Hardware Description Language (VHDL) code is written using the Altera MAX+Plus II environment to design, compile and simulate for each operation in...

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主要作者: Lee, Tiong Kiat
格式: Thesis
出版: 2003
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总结:The arithmetic logic unit (ALU) is designed to perform bit serial operation on two 8 bits input. In this project , a Very High Speed Integrated Circuit Hardware Description Language (VHDL) code is written using the Altera MAX+Plus II environment to design, compile and simulate for each operation in the bit serial arithmetic logic unit. The details of each design steps from design entry, compilation, debugging, simulation and syntheis is described in this project.