VLSI Design Of A Bit Serial Arithmetic Logic Unit
The arithmetic logic unit (ALU) is designed to perform bit serial operation on two 8 bits input. In this project , a Very High Speed Integrated Circuit Hardware Description Language (VHDL) code is written using the Altera MAX+Plus II environment to design, compile and simulate for each operation in...
Saved in:
主要作者: | |
---|---|
格式: | Thesis |
出版: |
2003
|
主題: | |
標簽: |
添加標簽
沒有標簽, 成為第一個標記此記錄!
|
成為第一個發表評論!