Synthesis of transistor chaining algorithm for CMOS cell layout using euler path / Sukri Hanafiah
The objective of this project is to build Optimal Layout of CMOS Functional Arrays 1C standard cell design. Firstly, this report is discussed about the Optimal Layout of CMOS Functional of CMOS functional array. Optimal Layout is the layout of the arrangment of CMOS transistor with the implementatio...
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| Main Author: | |
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| Format: | Thesis |
| Language: | English |
| Published: |
1997
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| Online Access: | https://ir.uitm.edu.my/id/eprint/100747/1/100747.pdf |
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| Summary: | The objective of this project is to build Optimal Layout of CMOS Functional Arrays 1C standard cell design. Firstly, this report is discussed about the Optimal Layout of CMOS Functional of CMOS functional array. Optimal Layout is the layout of the arrangment of CMOS transistor with the implementation of a random logic functional on an array of CMOS transistor. After discussing about the introduction (the basic of CMOS transistor ), we will discuss how to create the Optimal layout of CMOS Functional Array with the minimum separation based on euler path method. The euler's path it using pseudo input and Heuristic algorithm to find the minimum interlace. The comparison between euler's path and Bipartite graph Algorithm [14] will be made at the end this of this report to see which one give optimal chaining . |
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