Synthesis of transistor chaining algorithm for CMOS cell layout using bipartite graph / Azizi Misnan
This project implement a algonthm for the optimal transistor chaining problem in CMOS functional cell layout based on Uehara and vanCleemput's layout style [1] which assumed that the height of each logic module layout is constant and performed the optimisation by decomposing the graph module in...
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| 主要作者: | |
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| 格式: | Thesis |
| 語言: | English |
| 出版: |
1997
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| 在線閱讀: | https://ir.uitm.edu.my/id/eprint/101322/1/101322.pdf |
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