8-bit Successive Approximation Register Analog-to-Digital (SAR ADC) logic design / Zuhaila Abdul Halim

This thesis presents the design of a 8-bit Successive Approximation Register (S AR) logic of SAR ADC in a HP 0.5um SCN3M Complementary Metal Oxide Semiconductor (CMOS). The architecture of SAR logic consists of 3 modules which are shift register, register low-to-high and code register. From this arc...

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主要作者: Abdul Halim, Zuhaila
格式: Thesis
语言:English
出版: 2006
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在线阅读:https://ir.uitm.edu.my/id/eprint/98646/1/98646.pdf
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