Fabrication and chracterization of single and multilayer tunnel dielectrics for advanced floating gate flash memory

The floating gate device has been the workhorse for the non-volatile memory technology since the beginning of flash memory era. However, as the device is scaled down towards the realms of nanometer dimension, floating gate flash faces a very steep scaling path. The tunnel oxide scaling has a practic...

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Main Author:	Ramzan, Mat Ayub
Format:	Thesis
Language:	English
Subjects:	Floating gate device Tunnel dielectrics Flash memory Tunnel oxide
Online Access:	http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/44368/1/P.1-24.pdf http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/44368/2/Full%20Text.pdf
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spelling	my-unimap-443682016-12-08T02:19:45Z Fabrication and chracterization of single and multilayer tunnel dielectrics for advanced floating gate flash memory Ramzan, Mat Ayub Prof. Dr. Uda Hashim The floating gate device has been the workhorse for the non-volatile memory technology since the beginning of flash memory era. However, as the device is scaled down towards the realms of nanometer dimension, floating gate flash faces a very steep scaling path. The tunnel oxide scaling has a practical limit of approximately 8 nm due to data retention requirement. Therefore, the purpose of this work is to characterize and to assess the performances of single and multi-layer tunnel oxide, which primary focus is to further scale it beyond 8 nm. This study was carried out in two steps. Firstly, device I-V characteristics were simulated using the MATLAB software, based on the most recent compact physical model. Programming speed and data retention were calculated based on the simulated I-V curves. Secondly, MOS capacitors were then fabricated and characterized to validate the simulation result. The performance of single layer tunnel oxide has been successfully demonstrated. Its performance has been mainly evaluated from two perspectives, namely the programming time τprog, and data retention τret. The τprog for 4 nm single layer oxide and oxynitride were calculated to be 110 μs and 130 μs respectively, not too far off from 100 μs technological requirement. However, their τret performance was well below 10-year requirement, with both dielectrics just been able to achieve 3.1 and 4.6 year respectively. In that sense, one can conclude that both 4 nm single layer oxide and oxynitride have failed to comply with the requirement of 18 nm technology node. However, it has been proved that nitrided oxide could improve the τret of single layer SiO2. Furthermore, it has also been demonstrated that the thickness of a single layer oxide and oxynitride of 8.25 and 6.4 nm respectively, would be required to achieve the 10-year data retention requirement. It has also been shown that nitrided oxide could serve as an effective way of suppressing trap generation which in turn would suppress low field device leakages, especially in the form of SILC. In the case of multi-layer dielectrics, it has been shown that the best configuration is the one with the thinnest bottom SiO2 / thickest Si3N4. Device simulation shows that for 2 and 3-layer dielectrics, the τprog was in the range of 18 to 41 μs for the EOT of 4 to 8 nm, while experimentally it’s in the range of 2 to 104 μs. Taking τret requirement into consideration however reveals that only configurations with the EOT of 6 nm for both 2 and 3-layer dielectrics and 8 nm of 3-layer dielectric have successfully met the requirement for 18 nm technology nodes. Universiti Malaysia Perlis (UniMAP) 2014 Thesis en http://dspace.unimap.edu.my:80/xmlui/handle/123456789/44368 http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/44368/1/P.1-24.pdf 4ad3505d756a1d20bbb3863de99765d5 http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/44368/2/Full%20Text.pdf 729a6a0ae9ccfe28dd062088ef07ccb4 http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/44368/3/license.txt 8a4605be74aa9ea9d79846c1fba20a33 Floating gate device Tunnel dielectrics Flash memory Tunnel oxide School of Microelectronic Engineering
institution	Universiti Malaysia Perlis
collection	UniMAP Institutional Repository
language	English
advisor	Prof. Dr. Uda Hashim
topic	Floating gate device Tunnel dielectrics Flash memory Tunnel oxide
spellingShingle	Floating gate device Tunnel dielectrics Flash memory Tunnel oxide Ramzan, Mat Ayub Fabrication and chracterization of single and multilayer tunnel dielectrics for advanced floating gate flash memory
description	The floating gate device has been the workhorse for the non-volatile memory technology since the beginning of flash memory era. However, as the device is scaled down towards the realms of nanometer dimension, floating gate flash faces a very steep scaling path. The tunnel oxide scaling has a practical limit of approximately 8 nm due to data retention requirement. Therefore, the purpose of this work is to characterize and to assess the performances of single and multi-layer tunnel oxide, which primary focus is to further scale it beyond 8 nm. This study was carried out in two steps. Firstly, device I-V characteristics were simulated using the MATLAB software, based on the most recent compact physical model. Programming speed and data retention were calculated based on the simulated I-V curves. Secondly, MOS capacitors were then fabricated and characterized to validate the simulation result. The performance of single layer tunnel oxide has been successfully demonstrated. Its performance has been mainly evaluated from two perspectives, namely the programming time τprog, and data retention τret. The τprog for 4 nm single layer oxide and oxynitride were calculated to be 110 μs and 130 μs respectively, not too far off from 100 μs technological requirement. However, their τret performance was well below 10-year requirement, with both dielectrics just been able to achieve 3.1 and 4.6 year respectively. In that sense, one can conclude that both 4 nm single layer oxide and oxynitride have failed to comply with the requirement of 18 nm technology node. However, it has been proved that nitrided oxide could improve the τret of single layer SiO2. Furthermore, it has also been demonstrated that the thickness of a single layer oxide and oxynitride of 8.25 and 6.4 nm respectively, would be required to achieve the 10-year data retention requirement. It has also been shown that nitrided oxide could serve as an effective way of suppressing trap generation which in turn would suppress low field device leakages, especially in the form of SILC. In the case of multi-layer dielectrics, it has been shown that the best configuration is the one with the thinnest bottom SiO2 / thickest Si3N4. Device simulation shows that for 2 and 3-layer dielectrics, the τprog was in the range of 18 to 41 μs for the EOT of 4 to 8 nm, while experimentally it’s in the range of 2 to 104 μs. Taking τret requirement into consideration however reveals that only configurations with the EOT of 6 nm for both 2 and 3-layer dielectrics and 8 nm of 3-layer dielectric have successfully met the requirement for 18 nm technology nodes.
format	Thesis
author	Ramzan, Mat Ayub
author_facet	Ramzan, Mat Ayub
author_sort	Ramzan, Mat Ayub
title	Fabrication and chracterization of single and multilayer tunnel dielectrics for advanced floating gate flash memory
title_short	Fabrication and chracterization of single and multilayer tunnel dielectrics for advanced floating gate flash memory
title_full	Fabrication and chracterization of single and multilayer tunnel dielectrics for advanced floating gate flash memory
title_fullStr	Fabrication and chracterization of single and multilayer tunnel dielectrics for advanced floating gate flash memory
title_full_unstemmed	Fabrication and chracterization of single and multilayer tunnel dielectrics for advanced floating gate flash memory
title_sort	fabrication and chracterization of single and multilayer tunnel dielectrics for advanced floating gate flash memory
granting_institution	Universiti Malaysia Perlis (UniMAP)
granting_department	School of Microelectronic Engineering
url	http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/44368/1/P.1-24.pdf http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/44368/2/Full%20Text.pdf
_version_	1747836833433124864

Fabrication and chracterization of single and multilayer tunnel dielectrics for advanced floating gate flash memory

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