Design of a 1.8v successive approximation register analog-to-digital converter with low noise
The purpose of this thesis is to design a 1.8V 8-bit resolution Successive Approximation Register Analog to Digital Converter (SAR-ADC) that has low flicker noise performance. SAR-ADC circuit is one of the most frequently used circuits in many applications. Some application suffers from noise signal...
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| Format: | Thesis |
| Language: | English |
| Published: |
2010
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| Subjects: | |
| Online Access: | http://psasir.upm.edu.my/id/eprint/40928/1/FK%202010%2053R.pdf |
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