Design of a 1.8v successive approximation register analog-to-digital converter with low noise
The purpose of this thesis is to design a 1.8V 8-bit resolution Successive Approximation Register Analog to Digital Converter (SAR-ADC) that has low flicker noise performance. SAR-ADC circuit is one of the most frequently used circuits in many applications. Some application suffers from noise signal...
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| Format: | Thesis |
| Language: | English |
| Published: |
2010
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| Subjects: | |
| Online Access: | http://psasir.upm.edu.my/id/eprint/40928/1/FK%202010%2053R.pdf |
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| Summary: | The purpose of this thesis is to design a 1.8V 8-bit resolution Successive Approximation Register Analog to Digital Converter (SAR-ADC) that has low flicker noise performance. SAR-ADC circuit is one of the most frequently used circuits in many applications. Some application suffers from noise signals at low frequencies, for example in sensors which are used in Compressed Natural Gas Direct Injection (CNGDI). Analog designers constantly deal with the problem of noise since it is related to linearity, power dissipation and speed.
The main building blocks of the SAR-ADC consist of the Sample-and-Hold (S/H) Circuit, comparator, control logic unit and a Digital to Analog Converter (DAC). This research focuses on the design of the S/H circuit as it is the greatest contributor to flicker noise. The S/H circuit in this research uses a bootstrapped CMOS switch that allows for improved accuracy. To reduce flicker noise, two types of amplifiers are proposed to be incorporated in the design of the S/H circuit, namely the two stage operational amplifier and the folded cascode amplifier. After comparison between the two in terms of noise performance, the S/H employing the two stage amplifier is chosen for the SAR-ADC design. Moreover, this structure provides high stability, and rail to rail input signal.
Results from detailed simulation confirm that the SAR-ADC has low flicker noise. From simulation, input referred noise for both two stage operational amplifier and folded cascode amplifier are 18 nV/√Hz. The output noise for the folded cascode op-amp is 191µv/√Hz, while the two stage op-amp has output noise 36 µv/√Hz. Since the S/H circuit using the two stage amplifier has output noise less than that of the folded cascode operational amplifier, it is chosen for the design of the SAR-ADC operating at low frequencies (1Hz to 500 KHz). From simulation, the SAR-ADC employing the two stage S/H circuit shows sampling speeds of 1 MS/s, DNL at 0.45 LSB, INL at 0.58 LSB, SNR of 48 dB, power dissipation of 252 µW and an ENOB of 7.68-bit. All simulations were done in 0.18μm TSMC CMOS process technology. |
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