A Test Vector Minimization Algorithm Based On Delta Debugging For Post-Silicon Validation Of Pcie Rootport
In silicon hardware design, such as designing PCIe devices, design verification is an essential part of the design process, whereby the devices are subjected to a series of tests that verify the functionality. However, manual debugging is still widely used in post-silicon validation and is a major b...
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| 主要作者: | |
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| 格式: | Thesis |
| 語言: | English |
| 出版: |
2017
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| 主題: | |
| 在線閱讀: | http://eprints.usm.my/39524/1/Toh_Yi_Feng_24_Pages.pdf |
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