Clock Distribution Network Building Algorithm For Multiple Ips In System On A Chip

In this project, an algorithm is proposed and developed to build the global CDN that is used to distribute the clocks to all partitions in the SoC using the channels available between partitions. The conventional method of building the global CDN involves manual interventions which decrease the g...

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Main Author:	Tan , Tze Liang
Format:	Thesis
Language:	English
Published:	2017
Subjects:	TK1-9971 Electrical engineering Electronics Nuclear engineering
Online Access:	http://eprints.usm.my/39582/1/Tan_Tze_Liang_24_Pages.pdf
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id	my-usm-ep.39582
record_format	uketd_dc
spelling	my-usm-ep.395822019-04-12T05:25:07Z Clock Distribution Network Building Algorithm For Multiple Ips In System On A Chip 2017 Tan , Tze Liang TK1-9971 Electrical engineering. Electronics. Nuclear engineering In this project, an algorithm is proposed and developed to build the global CDN that is used to distribute the clocks to all partitions in the SoC using the channels available between partitions. The conventional method of building the global CDN involves manual interventions which decrease the global CDN building efficiency and increase the overall SoC design cycle. To solve this issue, an algorithm is proposed to automate the global CDN building process and at the same time obtain a balanced overall CDN not achieved by the conventional method. Other researches have proposed different CDN structures to simplify the design process but the proposals often sacrifice placement resources to achieve this. The algorithm first collects the partition clock latency numbers and other constraints needed as setup. When the setup is done, the global CDN is build and routed. The algorithm checks for clock skew and scenic routing issues before proceeding to shield the global CDN to prevent cross-talk issues. The algorithm is done when a final checking on the clock skew is done. The algorithm is tested on two different floorplans with varying size and available channels using three different clocks for each floorplan to ensure the accuracy of the algorithm. Finally, the global CDN build using the algorithm is evaluated based on the time needed to build the global CDN and the clock buffer numbers and areas used. The algorithm is shown to be able to reduce 50% of the global CDN design cycle and save 5% of clock buffer numbers and areas. The improvement achieved by the algorithm in this project shows the efficiency in designing the global CDN improved tremendously compared to conventional method. 2017 Thesis http://eprints.usm.my/39582/ http://eprints.usm.my/39582/1/Tan_Tze_Liang_24_Pages.pdf application/pdf en public masters Universiti Sains Malaysia Pusat Pengajian Kejuruteraan Elektrik dan Elektronik
institution	Universiti Sains Malaysia
collection	USM Institutional Repository
language	English
topic	TK1-9971 Electrical engineering Electronics Nuclear engineering
spellingShingle	TK1-9971 Electrical engineering Electronics Nuclear engineering Tan , Tze Liang Clock Distribution Network Building Algorithm For Multiple Ips In System On A Chip
description	In this project, an algorithm is proposed and developed to build the global CDN that is used to distribute the clocks to all partitions in the SoC using the channels available between partitions. The conventional method of building the global CDN involves manual interventions which decrease the global CDN building efficiency and increase the overall SoC design cycle. To solve this issue, an algorithm is proposed to automate the global CDN building process and at the same time obtain a balanced overall CDN not achieved by the conventional method. Other researches have proposed different CDN structures to simplify the design process but the proposals often sacrifice placement resources to achieve this. The algorithm first collects the partition clock latency numbers and other constraints needed as setup. When the setup is done, the global CDN is build and routed. The algorithm checks for clock skew and scenic routing issues before proceeding to shield the global CDN to prevent cross-talk issues. The algorithm is done when a final checking on the clock skew is done. The algorithm is tested on two different floorplans with varying size and available channels using three different clocks for each floorplan to ensure the accuracy of the algorithm. Finally, the global CDN build using the algorithm is evaluated based on the time needed to build the global CDN and the clock buffer numbers and areas used. The algorithm is shown to be able to reduce 50% of the global CDN design cycle and save 5% of clock buffer numbers and areas. The improvement achieved by the algorithm in this project shows the efficiency in designing the global CDN improved tremendously compared to conventional method.
format	Thesis
qualification_level	Master's degree
author	Tan , Tze Liang
author_facet	Tan , Tze Liang
author_sort	Tan , Tze Liang
title	Clock Distribution Network Building Algorithm For Multiple Ips In System On A Chip
title_short	Clock Distribution Network Building Algorithm For Multiple Ips In System On A Chip
title_full	Clock Distribution Network Building Algorithm For Multiple Ips In System On A Chip
title_fullStr	Clock Distribution Network Building Algorithm For Multiple Ips In System On A Chip
title_full_unstemmed	Clock Distribution Network Building Algorithm For Multiple Ips In System On A Chip
title_sort	clock distribution network building algorithm for multiple ips in system on a chip
granting_institution	Universiti Sains Malaysia
granting_department	Pusat Pengajian Kejuruteraan Elektrik dan Elektronik
publishDate	2017
url	http://eprints.usm.my/39582/1/Tan_Tze_Liang_24_Pages.pdf
_version_	1747820761100320768

Clock Distribution Network Building Algorithm For Multiple Ips In System On A Chip

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