Very Large Scale Integration Cell Based Path Extractor For Physical To Layout Mapping In Fault Isolation Work

Very Large Scale Integration Cell Based Path Extractor For Physical To Layout Mapping In Fault Isolation Work

Debug and diagnosis in post-silicon challenges the technological advancement in Physical-to-Layout Mapping capabilities. Areas that require such innovation are fault isolation work in failure analysis of semiconductor devices, at post-silicon stage. Since fault isolation work begins at Register Tran...

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書目詳細資料
主要作者:	Pragasam, Matthew
格式:	Thesis
語言:	English
出版:	2017
主題:	TK1-9971 Electrical engineering Electronics Nuclear engineering
在線閱讀:	http://eprints.usm.my/39594/1/MATTHEW_PRAGASAM_24_Pages.pdf
標簽:	添加標簽沒有標簽, 成為第一個標記此記錄!

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