A Study On Power Reduction Techniques For Comparator Based On Body Biasing
The growth of portable electronic devices in consumer market has led to the innovation of low power design. Furthermore, the scaling down of CMOS process technology has increased the transistor density. As a result, the device has higher functionality but more power is consumed per area unit. Hence...
Saved in:
主要作者: | Osman, Nor Fatihah |
---|---|
格式: | Thesis |
语言: | English |
出版: |
2014
|
主题: | |
在线阅读: | http://eprints.usm.my/40745/1/NOR_FATIHAH_BINTI_OSMAN_24_Pages.pdf |
标签: |
添加标签
没有标签, 成为第一个标记此记录!
|
相似书籍
-
Clock Gating Technique For Power Reduction In Digital Design
由: Khor, Peng Lim
出版: (2012) -
Improved Techniques For Power
Consumption Reduction In
Portable Two-Way Radio
由: Adrian, Lim Hooi Jin
出版: (2013) -
Peak To Average Power Ratio Reduction In
Wireless Orthogonal Frequency Division
Multiplexing
由: Wahab, Aeizaal Azman Abdul
出版: (2014) -
On The Analysis Of Mcm Systems Papr
Profiles And The Wp-Ofdm System Papr
Reduction Techniques
由: Zakaria, Jamaluddin
出版: (2013) -
Modified PWM Technique For Torque Ripples Reduction In
Three Phase PM BLDC Motors
由: Salah, Wael Abdel Muhdi Yacoup
出版: (2012)