Lna Ic Design For Cognitive Radio Implementation
This thesis presents a wideband inductorless three-stage common source (CS) low noise amplifier (LNA) with negative feedback for cognitive radio communication applications covering the range of 300 MHz to 10 GHz. Designed in Global Foundries’ 0.13 um CMOS process and through post-layout simulations...
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| 語言: | English |
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2013
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my-usm-ep.409212018-07-05T07:39:00Z Lna Ic Design For Cognitive Radio Implementation 2013 Cheong , Chee Han TK1-9971 Electrical engineering. Electronics. Nuclear engineering This thesis presents a wideband inductorless three-stage common source (CS) low noise amplifier (LNA) with negative feedback for cognitive radio communication applications covering the range of 300 MHz to 10 GHz. Designed in Global Foundries’ 0.13 um CMOS process and through post-layout simulations over the covered band, the minimum and maximum voltage gain is 10 dB and 12.1 dB respectively whereas noise figure of 3.9 to 5.1 dB. S11 < -8.5 dB for the covered band and S11 < -10 dB is achieved up to 8.7 GHz. IIP3 achieves a minimum of -0.5dBm and maximum of 0.8 dBm at pre-layout simulations. The power consumption is 36 mW at 1.2 V. The LNA occupies an area of 26 μm × 46 μm excluding pads and 672 μm × 233 μm with pads. 2013 Thesis http://eprints.usm.my/40921/ http://eprints.usm.my/40921/1/CHEONG_CHEE_HAN_24_pages.pdf application/pdf en public masters Universiti Sains Malaysia Pusat Pengajian Kejuruteraan Elektrik dan Elektronik |
| institution |
Universiti Sains Malaysia |
| collection |
USM Institutional Repository |
| language |
English |
| topic |
TK1-9971 Electrical engineering Electronics Nuclear engineering |
| spellingShingle |
TK1-9971 Electrical engineering Electronics Nuclear engineering Cheong , Chee Han Lna Ic Design For Cognitive Radio Implementation |
| description |
This thesis presents a wideband inductorless three-stage common source (CS) low noise amplifier (LNA) with negative feedback for cognitive radio communication applications covering the range of 300 MHz to 10 GHz. Designed in Global Foundries’ 0.13 um CMOS process and through post-layout simulations over the covered band, the minimum and maximum voltage gain is 10 dB and 12.1 dB respectively whereas noise figure of 3.9 to 5.1 dB. S11 < -8.5 dB for the covered band and S11 < -10 dB is achieved up to 8.7 GHz. IIP3 achieves a minimum of -0.5dBm and maximum of 0.8 dBm at pre-layout simulations. The power consumption is 36 mW at 1.2 V. The LNA occupies an area of 26 μm × 46 μm excluding pads and 672 μm × 233 μm with pads. |
| format |
Thesis |
| qualification_level |
Master's degree |
| author |
Cheong , Chee Han |
| author_facet |
Cheong , Chee Han |
| author_sort |
Cheong , Chee Han |
| title |
Lna Ic Design For Cognitive Radio Implementation |
| title_short |
Lna Ic Design For Cognitive Radio Implementation |
| title_full |
Lna Ic Design For Cognitive Radio Implementation |
| title_fullStr |
Lna Ic Design For Cognitive Radio Implementation |
| title_full_unstemmed |
Lna Ic Design For Cognitive Radio Implementation |
| title_sort |
lna ic design for cognitive radio implementation |
| granting_institution |
Universiti Sains Malaysia |
| granting_department |
Pusat Pengajian Kejuruteraan Elektrik dan Elektronik |
| publishDate |
2013 |
| url |
http://eprints.usm.my/40921/1/CHEONG_CHEE_HAN_24_pages.pdf |
| _version_ |
1747820839790706688 |