Modeling Of Vertical Side Chip Interconnect Technology For 3-Dimensional Packaging
In this miniaturization era, previously, shrinking the technology node was used in order to maintain and improve the electrical performance of a device. However, this method is getting difficult due to the limitation of Silicon (Si) atomic size of the material in designing the integrated circuit (IC...
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| 主要作者: | |
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| 格式: | Thesis |
| 語言: | English |
| 出版: |
2015
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| 主題: | |
| 在線閱讀: | http://eprints.usm.my/40931/1/TAN_AI_HEONG_24_pages.pdf |
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