Reusable Automated Agent For Universal Verification Methodology System Testbench
Pre-silicon verification process is an important cog in an application specific integrated chip design cycle. It is considered one of the biggest bottle-neck in modern day design projects. Thus, verification efficiency and productivity has gained a lot of attention lately and will be the driving fac...
Saved in:
| Main Author: | |
|---|---|
| Format: | Thesis |
| Language: | English |
| Published: |
2015
|
| Subjects: | |
| Online Access: | http://eprints.usm.my/40975/1/R._LOGEISH_RAJ_SO_RAJUMANIKAM_24_pages.pdf |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|