Reusable Automated Agent For Universal Verification Methodology System Testbench

Pre-silicon verification process is an important cog in an application specific integrated chip design cycle. It is considered one of the biggest bottle-neck in modern day design projects. Thus, verification efficiency and productivity has gained a lot of attention lately and will be the driving fac...

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Main Author:	Rajumanikam, R. Logeish Raj
Format:	Thesis
Language:	English
Published:	2015
Subjects:	TK7800-8360 Electronics
Online Access:	http://eprints.usm.my/40975/1/R._LOGEISH_RAJ_SO_RAJUMANIKAM_24_pages.pdf
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id	my-usm-ep.40975
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spelling	my-usm-ep.409752018-07-11T02:45:31Z Reusable Automated Agent For Universal Verification Methodology System Testbench 2015 Rajumanikam, R. Logeish Raj TK7800-8360 Electronics Pre-silicon verification process is an important cog in an application specific integrated chip design cycle. It is considered one of the biggest bottle-neck in modern day design projects. Thus, verification efficiency and productivity has gained a lot of attention lately and will be the driving factor of this research. The purpose of this research is to build a verification solution that actively promotes reusability and interoperability of verification components and improve the automation within the verification solution. These are identified as important concepts to improve verification efficiency and productivity. A state of the art UVM (Universal Verification Methodology) verification solution centered on these concepts is built for the sideband module of a hard memory controller. First, the verification requirements of the sideband module are investigated. Next, existing testbench solutions were evaluated for its reuse capabilities. This is followed by proposing and implementing a testbench architecture that highly reuses existing verification components and be reused friendly itself. Next, the architecture is improved to allow higher level of automation within the testbench. The implemented verification solution is then measured and analysed for its reusability and automation. The result obtained shows the implemented verification solution achieves a reusability of 21.70% in a system level testbench and 49.67% in the standalone sideband verification environment. In addition, the autonomous agent approach implemented in the architecture reduces the test writer's burden by at least 60% and up to 78%. 2015 Thesis http://eprints.usm.my/40975/ http://eprints.usm.my/40975/1/R._LOGEISH_RAJ_SO_RAJUMANIKAM_24_pages.pdf application/pdf en public masters Universiti Sains Malaysia Pusat Pengajian Kejuruteraan Elektrik dan Elektronik
institution	Universiti Sains Malaysia
collection	USM Institutional Repository
language	English
topic	TK7800-8360 Electronics
spellingShingle	TK7800-8360 Electronics Rajumanikam, R. Logeish Raj Reusable Automated Agent For Universal Verification Methodology System Testbench
description	Pre-silicon verification process is an important cog in an application specific integrated chip design cycle. It is considered one of the biggest bottle-neck in modern day design projects. Thus, verification efficiency and productivity has gained a lot of attention lately and will be the driving factor of this research. The purpose of this research is to build a verification solution that actively promotes reusability and interoperability of verification components and improve the automation within the verification solution. These are identified as important concepts to improve verification efficiency and productivity. A state of the art UVM (Universal Verification Methodology) verification solution centered on these concepts is built for the sideband module of a hard memory controller. First, the verification requirements of the sideband module are investigated. Next, existing testbench solutions were evaluated for its reuse capabilities. This is followed by proposing and implementing a testbench architecture that highly reuses existing verification components and be reused friendly itself. Next, the architecture is improved to allow higher level of automation within the testbench. The implemented verification solution is then measured and analysed for its reusability and automation. The result obtained shows the implemented verification solution achieves a reusability of 21.70% in a system level testbench and 49.67% in the standalone sideband verification environment. In addition, the autonomous agent approach implemented in the architecture reduces the test writer's burden by at least 60% and up to 78%.
format	Thesis
qualification_level	Master's degree
author	Rajumanikam, R. Logeish Raj
author_facet	Rajumanikam, R. Logeish Raj
author_sort	Rajumanikam, R. Logeish Raj
title	Reusable Automated Agent For Universal Verification Methodology System Testbench
title_short	Reusable Automated Agent For Universal Verification Methodology System Testbench
title_full	Reusable Automated Agent For Universal Verification Methodology System Testbench
title_fullStr	Reusable Automated Agent For Universal Verification Methodology System Testbench
title_full_unstemmed	Reusable Automated Agent For Universal Verification Methodology System Testbench
title_sort	reusable automated agent for universal verification methodology system testbench
granting_institution	Universiti Sains Malaysia
granting_department	Pusat Pengajian Kejuruteraan Elektrik dan Elektronik
publishDate	2015
url	http://eprints.usm.my/40975/1/R._LOGEISH_RAJ_SO_RAJUMANIKAM_24_pages.pdf
_version_	1747820851990888448

Reusable Automated Agent For Universal Verification Methodology System Testbench

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