Design Of Multiply-By-Two Amplifier For 1.5 Bit Pipelined Analogue-To-Digital Converter Application
This report explain about the design of multiply-by-two amplifier for Analogue-To-Digital Converter. The specification of the operational amplifier is 40dB of gain, and 1MHz cut-off frequency. Silterra 0.13um process technology is used in this work. The amplifier topology used in this research is Fo...
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2014
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my-usm-ep.410782018-07-17T08:37:11Z Design Of Multiply-By-Two Amplifier For 1.5 Bit Pipelined Analogue-To-Digital Converter Application 2014 Teng , Jin Chung TK7800-8360 Electronics This report explain about the design of multiply-by-two amplifier for Analogue-To-Digital Converter. The specification of the operational amplifier is 40dB of gain, and 1MHz cut-off frequency. Silterra 0.13um process technology is used in this work. The amplifier topology used in this research is Folded cascode which gives larger output swing. Differential pairs Common-mode feedback is used to overcome the mismatch of source current and to fix the folded cascode output voltage level at 350mV. The proposed design was able to achieve DC gain of 44.77dB and 1.06MHz cut-off frequency. The designed amplifier power consumption is very low, which is 9.598mW. Figure of merit of this design are 2014 Thesis http://eprints.usm.my/41078/ http://eprints.usm.my/41078/1/TENG_JIN_CHUNG_24_Pages.pdf application/pdf en public masters Universiti Sains Malaysia Pusat Pengajian Kejuruteraan Elektrik dan Elektronik |
| institution |
Universiti Sains Malaysia |
| collection |
USM Institutional Repository |
| language |
English |
| topic |
TK7800-8360 Electronics |
| spellingShingle |
TK7800-8360 Electronics Teng , Jin Chung Design Of Multiply-By-Two Amplifier For 1.5 Bit Pipelined Analogue-To-Digital Converter Application |
| description |
This report explain about the design of multiply-by-two amplifier for Analogue-To-Digital Converter. The specification of the operational amplifier is 40dB of gain, and 1MHz cut-off frequency. Silterra 0.13um process technology is used in this work. The amplifier topology used in this research is Folded cascode which gives larger output swing. Differential pairs Common-mode feedback is used to overcome the mismatch of source current and to fix the folded cascode output voltage level at 350mV. The proposed design was able to achieve DC gain of 44.77dB and 1.06MHz cut-off frequency. The designed amplifier power consumption is very low, which is 9.598mW. Figure of merit of this design are |
| format |
Thesis |
| qualification_level |
Master's degree |
| author |
Teng , Jin Chung |
| author_facet |
Teng , Jin Chung |
| author_sort |
Teng , Jin Chung |
| title |
Design Of Multiply-By-Two Amplifier For 1.5 Bit Pipelined Analogue-To-Digital Converter Application |
| title_short |
Design Of Multiply-By-Two Amplifier For 1.5 Bit Pipelined Analogue-To-Digital Converter Application |
| title_full |
Design Of Multiply-By-Two Amplifier For 1.5 Bit Pipelined Analogue-To-Digital Converter Application |
| title_fullStr |
Design Of Multiply-By-Two Amplifier For 1.5 Bit Pipelined Analogue-To-Digital Converter Application |
| title_full_unstemmed |
Design Of Multiply-By-Two Amplifier For 1.5 Bit Pipelined Analogue-To-Digital Converter Application |
| title_sort |
design of multiply-by-two amplifier for 1.5 bit pipelined analogue-to-digital converter application |
| granting_institution |
Universiti Sains Malaysia |
| granting_department |
Pusat Pengajian Kejuruteraan Elektrik dan Elektronik |
| publishDate |
2014 |
| url |
http://eprints.usm.my/41078/1/TENG_JIN_CHUNG_24_Pages.pdf |
| _version_ |
1747820872166539264 |