Study Of The Relationship Between Delta Delay And Adjacent Parallel Wire Length In 45 Nanometer Process Technology
Hierarchical design spans the complete framework of a design flow from Register Transfer Level (RTL), synthesis, place and route, timing closure and various other analyses before sign-off. Finer geometries and increasing interconnect density however have resulted signal integrity becoming the key is...
Saved in:
Main Author: | Mohamed, Shamsul Anuar |
---|---|
Format: | Thesis |
Language: | English |
Published: |
2014
|
Subjects: | |
Online Access: | http://eprints.usm.my/46237/1/Shamsul%20Anuar%20Bin%20Mohamed24.pdf |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
-
Interconnect delay and routing in nanometer VLSI
by: Kuay, Chong Lee
Published: (2008) -
A Test Vector Minimization Algorithm Based On Delta Debugging For Post-Silicon Validation Of Pcie Rootport
by: Toh , Yi Feng
Published: (2017) -
Experimental and investigation on parallel operation of three phase transformer for star-delta and delta-delta connections / Mohamad Hisyam Mansor
by: Mansor, Mohamad Hisyam
Published: (2000) -
Mipog : a parallel t-way minimization strategy for combinatorial testing
by: Al-Khiro, Mohammed Issam Younis
Published: (2010) -
Impact of nanometer transistor on analog performance
by: Husaini Zakaria, Mohamad Asfa
Published: (2011)