Numerical Analysis During Encapsulation Process Of Molded Underfill With Multi Flip Chip Package
Nowadays, the technology of Integrated Circuit (IC) packaging has become a sophisticated design in addition to maintaining reliability and quality. Flip Chip Scale Package (CSP) is one of the IC chips which has a wafer-level packaged with spherical solder bump located on a grid with a pre-defined pi...
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| Format: | Thesis |
| Language: | English |
| Published: |
2018
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| Online Access: | http://eprints.usm.my/46686/1/Numerical%20Analysis%20During%20Encapsulation%20Process%20Of%20Molded%20Underfill%20With%20Multi%20Flip%20Chip%20Package.pdf |
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