Thermal-safe system-on-chip test scheduling using dynamic voltage and frequency scaling
Designing integrated circuits (ICs) has become more challenging when fabrication technology scales down. Overheating has been acknowledged as a major issue in testing due to high power consumption of a chip during test. A direct consequence of the increasing power density is the increasing junction...
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| 主要作者: | |
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| 格式: | Thesis |
| 語言: | English |
| 出版: |
2018
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| 主題: | |
| 在線閱讀: | http://eprints.utm.my/id/eprint/102249/1/HaslizaHassanPSKE2018.pdf |
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