Register transfer level design of compression processor core using verilog hardware description language

Throughput independent and parameterized data compression processor core was designed to tackle the needs of high-speed data compression applications. The design is based on combination of LZSS algorithm and Huffman coding, which enables it to be used in compression of a wide variety of data types....

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Bibliographic Details
Main Author: Mohd. Sabri, Roslee
Format: Thesis
Published: 2007
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