APA引文

Mohd. Sabri, R. (2007). Register transfer level design of compression processor core using verilog hardware description language.

Chicago Style (17th ed.) Citation

Mohd. Sabri, Roslee. Register Transfer Level Design of Compression Processor Core Using Verilog Hardware Description Language. 2007.

MLA引文

Mohd. Sabri, Roslee. Register Transfer Level Design of Compression Processor Core Using Verilog Hardware Description Language. 2007.

警告：這些引文格式不一定是100％准確.