Mohd. Sabri, R. (2007). Register transfer level design of compression processor core using verilog hardware description language.
Chicago Style (17th ed.) CitationMohd. Sabri, Roslee. Register Transfer Level Design of Compression Processor Core Using Verilog Hardware Description Language. 2007.
MLA (8th ed.) CitationMohd. Sabri, Roslee. Register Transfer Level Design of Compression Processor Core Using Verilog Hardware Description Language. 2007.
Warning: These citations may not always be 100% accurate.