Register transfer level design of compression processor core using verilog hardware description language

Register transfer level design of compression processor core using verilog hardware description language

Throughput independent and parameterized data compression processor core was designed to tackle the needs of high-speed data compression applications. The design is based on combination of LZSS algorithm and Huffman coding, which enables it to be used in compression of a wide variety of data types....

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书目详细资料
主要作者:	Mohd. Sabri, Roslee
格式:	Thesis
语言:	English
出版:	2007
主题:	TK Electrical engineering Electronics Nuclear engineering
在线阅读:	http://eprints.utm.my/id/eprint/11398/1/RosleeMohdSabriMFKE2007.pdf
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