A computer aided design software module for clock tree synthesis in very large scale integration design

With the evolution of Very Large Scale Integration (VLSI) fabrication technology, circuit size has grown and line width has decreased. In effect, the transistor transit time and the time to drive signal lines across chips have also decreased. Thus, interconnections have become the dominating fact...

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Bibliographic Details
Main Author: Chew, Eik Wee
Format: Thesis
Language:English
Published: 2008
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Online Access:http://eprints.utm.my/id/eprint/17986/1/ChewEikWeeMFKE2008.pdf
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