Modified pattern generator of built-in self test for sequential circuits with reduced test time
محفوظ في:
| المؤلف الرئيسي: | |
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| التنسيق: | أطروحة |
| منشور في: |
2011
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| الموضوعات: | |
| الوسوم: |
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my-utm-ep.26858 |
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uketd_dc |
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my-utm-ep.268582017-07-10T07:19:55Z Modified pattern generator of built-in self test for sequential circuits with reduced test time 2011 Muhamad Amin, Muhamad Ridzuan Radin TK Electrical engineering. Electronics Nuclear engineering 2011 Thesis http://eprints.utm.my/id/eprint/26858/ http://libraryopac.utm.my/client/en_AU/main/search/results?qu=Modified+pattern+generator+of+built-in+self+test+for+sequential+circuits+with+reduced+test+time&te= masters Universiti Teknologi Malaysia, Faculty of Electrical Engineering Faculty of Electrical Engineering |
| institution |
Universiti Teknologi Malaysia |
| collection |
UTM Institutional Repository |
| topic |
TK Electrical engineering Electronics Nuclear engineering |
| spellingShingle |
TK Electrical engineering Electronics Nuclear engineering Muhamad Amin, Muhamad Ridzuan Radin Modified pattern generator of built-in self test for sequential circuits with reduced test time |
| description |
|
| format |
Thesis |
| qualification_level |
Master's degree |
| author |
Muhamad Amin, Muhamad Ridzuan Radin |
| author_facet |
Muhamad Amin, Muhamad Ridzuan Radin |
| author_sort |
Muhamad Amin, Muhamad Ridzuan Radin |
| title |
Modified pattern generator of built-in self test for sequential circuits with reduced test time |
| title_short |
Modified pattern generator of built-in self test for sequential circuits with reduced test time |
| title_full |
Modified pattern generator of built-in self test for sequential circuits with reduced test time |
| title_fullStr |
Modified pattern generator of built-in self test for sequential circuits with reduced test time |
| title_full_unstemmed |
Modified pattern generator of built-in self test for sequential circuits with reduced test time |
| title_sort |
modified pattern generator of built-in self test for sequential circuits with reduced test time |
| granting_institution |
Universiti Teknologi Malaysia, Faculty of Electrical Engineering |
| granting_department |
Faculty of Electrical Engineering |
| publishDate |
2011 |
| _version_ |
1747815528113635328 |