The RTL design of 32-bit RISC processor using verilog HDL
The objective of this research is to design a Reduced Instruction Set Computer (RISC) processor core based on ARM instruction set architecture for System-on-Chip (SoC) development design. The RISC computer architecture is selected because as it is accepted as the processor for mobile computing and i...
Saved in:
| Main Author: | |
|---|---|
| Format: | Thesis |
| Language: | English |
| Published: |
2012
|
| Subjects: | |
| Online Access: | http://eprints.utm.my/id/eprint/32631/5/HafizulHasniManabMFKE2012.pdf |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|