APA引文

Manab, H. H. (2012). The RTL design of 32-bit RISC processor using verilog HDL.

Chicago Style (17th ed.) Citation

Manab, Hafizul Hasni. The RTL Design of 32-bit RISC Processor Using Verilog HDL. 2012.

MLA引文

Manab, Hafizul Hasni. The RTL Design of 32-bit RISC Processor Using Verilog HDL. 2012.

警告：这些引文格式不一定是100％准确.