APA (7th ed.) Citation

Manab, H. H. (2012). The RTL design of 32-bit RISC processor using verilog HDL.

Chicago Style (17th ed.) Citation

Manab, Hafizul Hasni. The RTL Design of 32-bit RISC Processor Using Verilog HDL. 2012.

MLA (8th ed.) Citation

Manab, Hafizul Hasni. The RTL Design of 32-bit RISC Processor Using Verilog HDL. 2012.

Warning: These citations may not always be 100% accurate.