The RTL design of 32-bit RISC processor using verilog HDL
The objective of this research is to design a Reduced Instruction Set Computer (RISC) processor core based on ARM instruction set architecture for System-on-Chip (SoC) development design. The RISC computer architecture is selected because as it is accepted as the processor for mobile computing and i...
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| Format: | Thesis |
| Language: | English |
| Published: |
2012
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| Online Access: | http://eprints.utm.my/id/eprint/32631/5/HafizulHasniManabMFKE2012.pdf |
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| Summary: | The objective of this research is to design a Reduced Instruction Set Computer (RISC) processor core based on ARM instruction set architecture for System-on-Chip (SoC) development design. The RISC computer architecture is selected because as it is accepted as the processor for mobile computing and in SoC based design computing system. Moreover, it reduces processor complexity by reducing its instruction set from highly complex microprogrammed instruction set into a limited number of instruction that can completely executes one instruction in one cycle. As System on Chip (SoC) becomes an amazing solution in various applications such as hardware accelerator for video and image processing system in an embedded system, importance of microprocessor design in SoC increases for developing an optimal embedded system which are fast, small memory size, and low power consumption. |
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