The RTL design of 32-bit RISC processor using verilog HDL

The objective of this research is to design a Reduced Instruction Set Computer (RISC) processor core based on ARM instruction set architecture for System-on-Chip (SoC) development design. The RISC computer architecture is selected because as it is accepted as the processor for mobile computing and i...

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主要作者:	Manab, Hafizul Hasni
格式:	Thesis
語言:	English
出版:	2012
主題:	QA75 Electronic computers Computer science
在線閱讀:	http://eprints.utm.my/id/eprint/32631/5/HafizulHasniManabMFKE2012.pdf
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id	my-utm-ep.32631
record_format	uketd_dc
spelling	my-utm-ep.326312018-05-27T07:46:56Z The RTL design of 32-bit RISC processor using verilog HDL 2012-01 Manab, Hafizul Hasni QA75 Electronic computers. Computer science The objective of this research is to design a Reduced Instruction Set Computer (RISC) processor core based on ARM instruction set architecture for System-on-Chip (SoC) development design. The RISC computer architecture is selected because as it is accepted as the processor for mobile computing and in SoC based design computing system. Moreover, it reduces processor complexity by reducing its instruction set from highly complex microprogrammed instruction set into a limited number of instruction that can completely executes one instruction in one cycle. As System on Chip (SoC) becomes an amazing solution in various applications such as hardware accelerator for video and image processing system in an embedded system, importance of microprocessor design in SoC increases for developing an optimal embedded system which are fast, small memory size, and low power consumption. 2012-01 Thesis http://eprints.utm.my/id/eprint/32631/ http://eprints.utm.my/id/eprint/32631/5/HafizulHasniManabMFKE2012.pdf application/pdf en public masters Universiti Teknologi Malaysia, Faculty of Electrical Engineering Faculty of Electrical Engineering
institution	Universiti Teknologi Malaysia
collection	UTM Institutional Repository
language	English
topic	QA75 Electronic computers Computer science
spellingShingle	QA75 Electronic computers Computer science Manab, Hafizul Hasni The RTL design of 32-bit RISC processor using verilog HDL
description	The objective of this research is to design a Reduced Instruction Set Computer (RISC) processor core based on ARM instruction set architecture for System-on-Chip (SoC) development design. The RISC computer architecture is selected because as it is accepted as the processor for mobile computing and in SoC based design computing system. Moreover, it reduces processor complexity by reducing its instruction set from highly complex microprogrammed instruction set into a limited number of instruction that can completely executes one instruction in one cycle. As System on Chip (SoC) becomes an amazing solution in various applications such as hardware accelerator for video and image processing system in an embedded system, importance of microprocessor design in SoC increases for developing an optimal embedded system which are fast, small memory size, and low power consumption.
format	Thesis
qualification_level	Master's degree
author	Manab, Hafizul Hasni
author_facet	Manab, Hafizul Hasni
author_sort	Manab, Hafizul Hasni
title	The RTL design of 32-bit RISC processor using verilog HDL
title_short	The RTL design of 32-bit RISC processor using verilog HDL
title_full	The RTL design of 32-bit RISC processor using verilog HDL
title_fullStr	The RTL design of 32-bit RISC processor using verilog HDL
title_full_unstemmed	The RTL design of 32-bit RISC processor using verilog HDL
title_sort	rtl design of 32-bit risc processor using verilog hdl
granting_institution	Universiti Teknologi Malaysia, Faculty of Electrical Engineering
granting_department	Faculty of Electrical Engineering
publishDate	2012
url	http://eprints.utm.my/id/eprint/32631/5/HafizulHasniManabMFKE2012.pdf
_version_	1747816049316724736

The RTL design of 32-bit RISC processor using verilog HDL

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