Software-based self-testing for a risc processor
Software-based self-testing (SBST) has been touted as the effective way to test the processors effectively, with reasonable test coverage, plus the advantages of at-speed testing, and without performance degradation in terms of area and power. Previous work has been done on combining SBST with parti...
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2014
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my-utm-ep.486172020-03-02T07:24:04Z Software-based self-testing for a risc processor 2014 Teh, Wee Meng QA76 Computer software Software-based self-testing (SBST) has been touted as the effective way to test the processors effectively, with reasonable test coverage, plus the advantages of at-speed testing, and without performance degradation in terms of area and power. Previous work has been done on combining SBST with partial scan logic insertion at Register Transfer Language (RTL) level for a 16-bit RISC processor design. In this project, focus will be done on test coverage improvement without the use of scan logic. 2014 Thesis http://eprints.utm.my/id/eprint/48617/ http://eprints.utm.my/id/eprint/48617/1/TehWeeMengMFKE2014.pdf application/pdf en public http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:82137?queryType=vitalDismax&query=Software-based+self-testing+for+a+risc+processor&public=true masters Universiti Teknologi Malaysia, Faculty of Electrical Engineering Faculty of Electrical Engineering |
| institution |
Universiti Teknologi Malaysia |
| collection |
UTM Institutional Repository |
| language |
English |
| topic |
QA76 Computer software |
| spellingShingle |
QA76 Computer software Teh, Wee Meng Software-based self-testing for a risc processor |
| description |
Software-based self-testing (SBST) has been touted as the effective way to test the processors effectively, with reasonable test coverage, plus the advantages of at-speed testing, and without performance degradation in terms of area and power. Previous work has been done on combining SBST with partial scan logic insertion at Register Transfer Language (RTL) level for a 16-bit RISC processor design. In this project, focus will be done on test coverage improvement without the use of scan logic. |
| format |
Thesis |
| qualification_level |
Master's degree |
| author |
Teh, Wee Meng |
| author_facet |
Teh, Wee Meng |
| author_sort |
Teh, Wee Meng |
| title |
Software-based self-testing for a risc processor |
| title_short |
Software-based self-testing for a risc processor |
| title_full |
Software-based self-testing for a risc processor |
| title_fullStr |
Software-based self-testing for a risc processor |
| title_full_unstemmed |
Software-based self-testing for a risc processor |
| title_sort |
software-based self-testing for a risc processor |
| granting_institution |
Universiti Teknologi Malaysia, Faculty of Electrical Engineering |
| granting_department |
Faculty of Electrical Engineering |
| publishDate |
2014 |
| url |
http://eprints.utm.my/id/eprint/48617/1/TehWeeMengMFKE2014.pdf |
| _version_ |
1747817434150076416 |