Graph processing hardware accelerator for shortest path algorithms in nanometer very large-scale integration interconnect routing

Graph processing hardware accelerator for shortest path algorithms in nanometer very large-scale integration interconnect routing

Graphs are pervasive data structures in computer science, and algorithms working with them are fundamental to the field. Many challenging problems in Very Large-Scale Integration (VLSI) physical design automation are modeled using graphs. The routing problems in VLSI physical design are, in essence,...

وصف كامل

محفوظ في:

التفاصيل البيبلوغرافية
المؤلف الرئيسي:	Ch'ng, Heng Sun
التنسيق:	أطروحة
اللغة:	English
منشور في:	2007
الموضوعات:	TK Electrical engineering Electronics Nuclear engineering
الوصول للمادة أونلاين:	http://eprints.utm.my/id/eprint/6381/1/ChNgHengSunMFKE2007.pdf
الوسوم:	إضافة وسم لا توجد وسوم, كن أول من يضع وسما على هذه التسجيلة!

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