Modeling and analysis of cylindrical gate-all around silicon nanowire FET including BOHM quantum potential model
According to Moores’s Law, the number of transistors per square inch on integrated circuits are doubled every year. Now, the transistors size has been scaled down to 15nm. The smaller the transistors size gives more space for transistors to be added in system on chip (SoC) thus will provide a lot of...
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| 格式: | Thesis |
| 語言: | English |
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2018
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| 主題: | |
| 在線閱讀: | http://eprints.utm.my/id/eprint/78859/1/MuhammadAtifAbdRazakMFKE2018.pdf |
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