Design for testability method at register transfer level
The testing of sequential circuit is more complex compared to combinational circuit because it needs a sequence of vectors to detect a fault. Its test cost increases with the complexity of the sequential circuit-under-test (CUT). Thus, design for testability (DFT) concept has been introduced to redu...
Saved in:
| 主要作者: | |
|---|---|
| 格式: | Thesis |
| 語言: | English |
| 出版: |
2016
|
| 主題: | |
| 在線閱讀: | http://eprints.utm.my/id/eprint/81731/1/NorlinaParamanPFKE2016.pdf |
| 標簽: |
添加標簽
沒有標簽, 成為第一個標記此記錄!
|